1. Field of the Invention
This invention relates to memory cell arrays, and more particularly to arrays of electrically erasable and programmable memory cells which are based on Fowler-Nordheim tunneling.
2. Background of the Invention
One of the important factors for a successful memory design is minimization of the size of the memory array. Flash EEPROM (electrically erasable and programmable read-only memory) technology provides a cell size similar to EPROM (erasable programmable read-only memory) technology as well as electrical erasability.
Because EEPROM devices are electrically erasable, they do not require the expensive ceramic-quartz window packages used for conventional EPROM devices. On the other hand, electrical erasing can leave the floating gate positively charged, converting the memory transistor into a depletion mode transistor.
Techniques have been developed to avoid positively charging the floating gate during erasure. One technique known as adaptive erasure uses an algorithm to control the amount of charge applied to the memory transistor during erasure. Unfortunately, adaptive erasure has the disadvantage of being relatively slow and difficult to implement in large memory arrays. Another approach uses a cell that comprises a floating gate memory transistor similar to an EPROM cell connected in series with a simple enhancement transistor controlled by the word line. This cell, which is more fully described in Samachisa et al, "A 128K Flash EEPROM Using Double-Polysilicon Technology," IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 676-683, avoids leakage current during programming and reading because of the action of the series enhancement transistor. The EPROM device in the cell is erased using Fowler-Nordheim tunneling and programmed using hot-electron injection, which is typical for EPROM devices. Unfortunately, the presence of the series enhancement transistor increases the size of the Flash EEPROM cell of Samachisa et al.
Given the considerable commercial importance placed on small memory size, further miniaturization in cell and array size is desirable.